One type of prior art non-volatile computer memory is the Erasable Programmable Read-Only Memory ("EPROM"). The EPROM can be programmed by a user. Once programmed, the EPROM retains its data until erased. Ultraviolet light erasure of the EPROM erases the entire contents of the memory. The memory may then be reprogrammed with new data.
One type of prior art computer memory package contains content addressable memory ("CAM") in addition to a main memory array. The main memory array is an EPROM memory, but the content addressable memory is formed by EPROM-type cells that are covered with a layer of metal. This metal layer blocks ultraviolet light from shining on the cells. Therefore, once the CAM cells are programmed, they cannot be erased by ultraviolet light. The CAM cells are thus permanently programmed. The CAM cells are of the type of memory called Unerasable Programmable Read-Only Memory ("UPROM").
In one type of prior art computer memory, the CAM cells are used to perform certain configuration and management functions. The CAM cells are programmed before the memory package reaches the end user as a final product. The CAM cells can be programmed to configure the memory device with respect to the device operation (for example, latched inputs, CEBTTL active high, OEBTTL active high, etc.). The CAM cells can also be used to activate (or deactivate) redundancy cells with respect to the main memory array. The redundancy cells are used in place of defective cells of the main memory array.
FIG. 1 is a circuit diagram of one prior art CAM cell. The CAM cell is formed by two N type of EPROM transistors 1 and 2. Transistors 1 and 2 each have floating gates. The floating gates physically reside underneath the control gates of the transistors. Transistors 5 and 7 are controlled by signals ENABLE 1 and ENABLE 2 to apply a high voltage of 12V to the drain of transistors 1 and 2 respectively.
Initially, both transistors 1 and 2 are in the erased state. In the erased state, transistors 1 and 2 are each in the conducting state. To program the CAM cell to a logical "zero" state, a high voltage of 12 volts is applied to the control gate transistor 1. The 12 volt high voltage is also applied to the drain of transistor 1 via transistor 5 by the active high ENABLE 1 signal applied to the gate of transistor 5. This results in electrons being deposited on the floating gate of transistor 1. The electrons deposited on the floating gate of transistor 1 cause the threshold of transistor 1 to be raised. This causes transistor 1 to become non-conducting, which causes the CAM cell output to be a logical "zero." Similarly, to program the CAM cell to a logical "one" state, the high voltage is applied to the control gate and drain of transistor 2. This causes transistor 2 to become non-conducting, which in turn makes the CAM cell output a logical "one" output signal.
For EPROM cells that are not CAM's, the application of ultraviolet light to the gates of the transistors programmed to a logical zero state would remove the electrons deposited on the floating gates of those transistors, and the transistors would switch from the non-conducting state to the conducting state. For the prior art CAM cell of FIG. 1, however, a metal layer 6 covers the gates of transistors 1 and 2 and prevents ultraviolet light from striking the gates of transistors 1 and 2. This prevents transistors 1 and 2 from being erased once transistors 1 and 2 are programmed to a logical zero state.
In the prior art, EPROMs are used in various types of systems, including systems wherein extremely low power consumption is required. To lower the power consumption of the EPROM, certain prior art EPROMs can be placed in a standby mode during the times the EPROMs are not being accessed. In the standby mode, certain internal circuits of the EPROMs are powered down. This significantly reduces the power consumption of the EPROMs. The standby mode is triggered by applying a high voltage of Vcc to the "chip enable" pin of the particular EPROM.
Before at least one prior art EPROM is shipped by the manufacturer, a series of tests are conducted to determine whether the EPROM meets its device specifications. Two of the specifications relate to standby current and standby power of the EPROM when the EPROM is in the standby mode. The EPROMs not meeting the specifications as to standby current and standby power are rejected.
Disadvantages are associated with the testing of standby current and standby power before the above-referenced prior art EPROMs are shipped. If the CAM cells of the EPROM device are not programmed before the device is tested, then standby current and standby power cannot be accurately measured. This follows from the fact that when the CAM cells are erased, they are all in the logical one state and are conducting. Each CAM cell that is programmed becomes non-conducting, however. Thus the programming of CAM cells changes the standby current and power.
On the other hand, if the CAM cells are programmed before the EPROM is tested, then standby current and standby power can be accurately measured. But the CAM cells once programmed cannot be reprogrammed. This may restrict the uses of the EPROM available to end users. Furthermore, the programming of the CAM cells is time-consuming and increases the cost of the EPROM. Moreover, if the standby current and standby power of the device tested does not meet the specifications, then the EPROM is rejected and the time-consuming programming has been spent on a rejected device.